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ASPLOS'22 - Session 8A - REVAMP: A Systematic Framework for Heterogeneous CGRA Realization
ASPLOS'22 - Session 8A - PLD: Fast FPGA Compilation to Make Reconfigurable Acceleration Compatible
ASPLOS'22 - Session 8A - Debugging in the Brave New World of Reconfigurable Hardware
ASPLOS'22 - Session 8A - CryoWire: Wire-Driven Microarchitecture Designs for Cryogenic Computing
ASPLOS'22 - Session 8A - Temporal and SFQ Pulse-Streams Encoding for Area-Efficient Superconducting
ASPLOS'23 - Session 8A - CaQR: A Compiler-assisted Approach for Qubit Reuse Through Dynamic Circuit
ASPLOS'23 - Session 8A - Better Than Worst-Case Decoding for Quantum Error Correction
ASPLOS'22 - Session 8B - Vector Instruction Selection for Digital Signal Processors Using Program
ASPLOS'22 - Session 9B - Taurus: A Data Plane Architecture for Per-Packet ML
ASPLOS'22 - Session 8B - CirFix: Automatically Repairing Defects in Hardware Design Code
ASPLOS'22 - Session 2A - ValueExpert: Exploring Value Patterns in GPU-accelerated Applications
ASPLOS'22 - Session 1B - CARAT CAKE: Replacing Paging via Compiler/Kernel Cooperation